I am an AI performance and systems engineer with more than a decade at the intersection of computer architecture, AI infrastructure, and high-performance computing. Most recently, in Intel's Datacenter Group, I characterized large language model and vision-language-action (VLA) robotics workloads end to end and turned that analysis into architecture direction: hands-on profiling on A100 and H200, roofline-based projection across edge accelerators, and the memory-bandwidth-versus-compute tradeoffs that decide real-time serving budgets. I led the adaptation of an LLM roofline performance simulator to multimodal workloads and was technical lead of a SPEC Cloud simulation effort advising AMD, Arm, and Google. Earlier, I led the Harvard–Intel graph-learning acceleration research that produced peer-reviewed papers, a US patent application, and optimizations upstreamed into PyTorch Geometric, and co-developed low-precision machine translation that won the 2020 WNGT efficiency task, with its INT8 kernels later adopted into SPEC CPU. My background is in physics and HPC: five years at EPCC supporting scientific applications on the UK national supercomputer, where I also organized an MSc course, co-developed a supercomputing MOOC, and led a UK-wide training program. The through-line is the same everywhere: balancing FLOP/s against TB/s at every layer of the memory hierarchy, and being clear about what is measured versus what is projected.
Characterized LLM and VLA serving (π0.x) end to end: model structure, attention behavior, matmul sizes, and BF16/INT8 execution, with hands-on profiling on A100 and H200 and roofline-based projection across edge accelerators. Led the adaptation of an LLM roofline performance simulator to multimodal workloads, supporting arbitrary inference configurations including disaggregated prefill/decode serving. Hand-optimized an INT8 GEMM on a pre-production dataflow accelerator via its native API. Aggregated workload-versus-hardware data (memory capacity and bandwidth, FLOPS, FLOPS/W) across GPUs, NPUs, and dataflow accelerators that informed architecture decisions. Technical lead of a five-person SPEC Cloud simulation and performance-projection effort advising AMD, Arm, and Google.
Coordinated research with scientists on GNNs, LLMs, and recommendation systems, connecting sparsity, memory-access patterns, and data movement to accelerator design choices. Established and led the Harvard–Intel graph-learning acceleration collaboration (about seven contributors across Intel and Harvard SEAS): IEEE ISPASS 2023, TASK Quarterly 2024, US Patent Application 18/325,348, and the HGAM optimization upstreamed into PyTorch Geometric (trim_to_layer) and pyg-lib.
Led workload enablement and characterization for Intel PiUMA during early evaluation: simulation on internal cycle-approximate architecture simulators, profiling, microbenchmarking, and GNN scalability analysis, correlating projections against pre-production prototype hardware (IEEE ISPASS 2023). Co-developed CPU-efficient INT8 and logarithmic 4-bit Marian neural machine translation with the University of Edinburgh (K. Heafield), winning the 2020 WNGT efficiency task; the open-source INT8 GEMM kernels were later adopted into SPEC CPU (2026).
HPC and data-science consulting across finance, cyber security, and exascale academia–industry collaborations. Built system-level workload characterization of ARCHER, the UK national supercomputer, profiling high-usage scientific applications (CASTEP, CP2K, VASP, GROMACS), and researched data-aware scheduling for Intel 3D XPoint non-volatile memory on the EU NextGenIO project. Modernized codes for Xeon and Xeon Phi at the Intel Parallel Computing Centre. Led EPCC's training activities (see Teaching).
Characterized VLA serving (π0.x) across model structure, attention behavior, transformer-diffusion balance, and BF16/INT8 execution; hands-on profiling on A100/H200 with roofline-based projection across Jetson-class edge, NPU, and dataflow accelerators. Isolated a memory-bandwidth-bound denoising loop that inverted compute-centric optimization priorities. Recommended lower-bit quantization and microscaling formats for real-time budgets; scoped world models as the next physical-AI workload wave.
Led the adaptation of an existing LLM roofline performance simulator to vision and VLA workloads. The simulator supports arbitrary inference configurations: model architectures, parallelism strategies, attention variants, and disaggregated prefill/decode serving; its analysis feeds architecture direction.
Technical lead of a five-person effort reconciling measured benchmark behavior against modeled results and advising consortium participants including AMD, Arm, and Google.
Established and led a cross-organization collaboration — around seven contributors across Intel and Harvard University (SEAS) — on graph-learning acceleration for Intel PiUMA. Owned inception, stakeholder management, software development and performance optimization — resulting in ISPASS 2023, a TASK Quarterly journal paper (2024) and a US patent application.
Part of the Intel–University of Edinburgh collaboration (K. Heafield) on CPU-efficient, low-precision (int8) Marian neural machine translation, which won the 2020 NGT efficiency task. The underlying int8 GEMM kernels were adopted into the SPEC CPU benchmark in 2026 — where Marian machine translation is the sole NLP workload.
Assessed silicon-photonics and rack-scale optical interconnect options for memory-centric inference, including commercial silicon-photonics interconnect solutions, comparing latency, throughput and cost across on- vs off-chip solutions; explored disaggregated compute/memory.
Built system-level workload characterization of ARCHER (UK national supercomputer) and researched data-aware, workflow-enabled HPC scheduling (SLURM-class) for Intel 3D XPoint non-volatile memory.
Designed and optimized the software stack of a custom GPU cluster — Highest LINPACK at ISC'14 (3.38 TFLOP/s/kW, est. 4th on the June 2014 Green500). Ported GADGET-3 kernels to GPU via OpenACC for 2× speedup.
Coordinated a team of eight lecturers across curriculum planning, delivery, assessment, and course management; also lectured, and taught Introduction to C++ and Java as a TA.
Co-developed EPCC's first MOOC: assisted content planning and produced all video recording and editing for the five-week self-paced course; 3,200+ registrations on the first run; presented the approach at the ISC'17 PRACE Training Workshop.
Planned, organized, and coordinated instructor-led workshops at Imperial College, UCL, EPCC, and beyond, training 250+ researchers in good software practice. Also led the ARCHER Diversity in HPC outreach project.
Pearson Tests of English speaking examiner (B1–C2); co-director, senior teacher, and exams coordinator at a language school, designing tiered curricula (CEFR A1–C2).